浮点加法器的低功耗结构设计  

Design of a Low Power Architecture for Floating-Point Adders

作　　者：高海霞[1] 杨银堂[1] 

机构地区：[1]西安电子科技大学微电子研究所,陕西西安710071

出　　处：《微电子学》2002年第2期128-130,135,共4页Microelectronics

摘　　要：浮点加法器是集成电路数据通道中重要的单元 ,它的性能和功耗极大地影响着处理器和数字信号处理器的性能。文章分析了浮点加法器的几种结构 ,重点介绍了实现低功耗的三数据通道结构。最后 。Floating point adder is an important block in IC datapaths Its performance and power consumptions have a great effect on the performance of processors and DSP's In this paper, several architectures for floating point adder are summarized and analyzed A low power triple datapath architecture is described in particular Finally, the practicability of floating point adder architecture has been analyzed

关 键 词：浮点加法器 低功耗 结构设计 数字信号处理器 数据通道 数字集成电路 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]