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作 者:D.Suresh K.K.Nagarajan R.Srinivasan
机构地区:[1]ECE Department,Sri Sivasubramaniya Nadar (SSN) College of Engineering [2]IT Department,Sri Sivasubramaniya Nadar (SSN) College of Engineering
出 处:《Journal of Semiconductors》2015年第4期104-109,共6页半导体学报(英文版)
基 金:supported by the Defense Research Development Organization(DRDO),Government of India
摘 要:The effect of process variations of a FinFET-based low noise amplifier (LNA) are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate (IDDG) FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance (the desired value is 50 f2 purely real) of the LNA is compensated by the second gate bias of the IDDG FinFET.The effect of process variations of a FinFET-based low noise amplifier (LNA) are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate (IDDG) FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance (the desired value is 50 f2 purely real) of the LNA is compensated by the second gate bias of the IDDG FinFET.
关 键 词:FINFET LNA process variation T-SPICE
分 类 号:TN722.3[电子电信—电路与系统]
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