低功耗三输入AND/XOR门的设计  

Low Power 3-Input AND/XOR Gate Design

作　　者：梁浩[1] 夏银水[1] 钱利波[1] 黄春蕾[1] 

机构地区：[1]宁波大学信息科学与工程学院,宁波315211

出　　处：《计算机辅助设计与图形学学报》2015年第5期940-945,共6页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金重点项目(61131001);国家自然科学基金(61228105;61404077)

摘　　要：三输入AND/XOR门是Reed-Muller(RM)逻辑电路的一种基本复合门电路单元.针对现有AND/XOR门电路由AND门和XOR/XNOR门级联而成,导致电路延时长、功耗大等问题,提出一种晶体管级的CMOS逻辑和传输逻辑混合的低功耗三输入AND/XOR门电路.首先在55nm CMOS工艺下,对所设计电路进行原理图和版图设计;然后对版图进行寄生参数提取,并在不同工艺角下与基于典型级联结构的电路进行后仿真分析和比较.实验结果表明,在典型工艺角下,所提出的电路的面积、功耗和功耗延迟积的改进最高分别达到18.79%,26.67%与31.25%.3-input AND/XOR gate is the basic complex gate for Reed-Muller （RM） logic circuit implementation. To cope with the issues of the present AND and XOR cascaded AND/XOR gate with long delay time and high power, a transistor-level based low power 3-input AND/XOR gate, which is implemented with hybrid logic of CMOS logic and transmit logic, is proposed.First,under 55nm CMOS process, the circuit schematic is proposed and its layout is implemented. Then, the parasitic parameter extraction based on the circuit layout and the post-simulations under different process corners are carried out. Under typical process corners, the simulation results show that, the improvement of the proposed circuit can be up to 18.79%, 26.67% and 31.25% respectively in terms of the area, power and power delay product compared with the classical cascaded designs.

关 键 词：AND/XOR门 Reed-Muller逻辑 低功耗 功耗延迟积 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]