三输入高性能AND/XOR复合门电路设计  

The design of three-input high-performance AND/XOR complex-gate circuit

作　　者：黄春蕾[1] 王伦耀[1] 梁浩[1] 夏银水[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《浙江大学学报（理学版）》2015年第3期310-315,共6页Journal of Zhejiang University（Science Edition）

基　　金：国家自然科学基金资助项目(61131001;61228105;61471211);教育部博士点基金资助项目(20113305110001);宁波市自然科学基金资助项目(2013A610009)

摘　　要：针对现有"与/异或"(AND/XOR)复合门级联设计电路存在功耗大、延时长等不足,提出一种基于晶体管级的三输入AND/XOR复合门电路结构.通过采用多轨结构、缩短传输路径以及混合CMOS逻辑设计方法,克服了原有电路中单一逻辑和单轨结构信号路径长的不足,进而提高了电路性能.在55nm的CMOS技术工艺和PTM多种工艺下,经过HSPICE模拟和Cadence提取版图的后仿真,显示所设计的电路具有正确的逻辑功能,相较于采用门电路级联而成的AND/XOR电路,本电路在不同负载、频率和PVT组合等情况下的延时、功耗和功耗延迟积(PDP)都得到了明显改善.Focusing on the problems of the high power consumption and time delay caused by gates cascading in the existing AND/XOR complex gate designs, a novel transistor-level three-input AND/XOR complex gate is proposed. The multi-rails structure and hybrid-CMOS techniques are employed in the design in order to short the signal trans- mission path and improve working speed. Compared to the published single-rail based complex gates, the perform- ance of the proposed design is improved in power and delay. The proposed complex gate is tested under 55 nm CMOS technology and the posting-simulations using HSPICE and Cadence under PTM technologies show that the proposed circuit has correct logic function, and the power and power delay product （PDP） are obviously improved under various loads, frequencies and PVTs.

关 键 词：与/异或 混合CMOS逻辑 多轨结构 功耗延迟积 晶体管级 

分 类 号：TN4[电子电信—微电子学与固体电子学] TN431.2