基于FPGA的TPC编译码器设计与实现  

Design and Realization of TPC Coding Based on FPGA

作　　者：李超[1] 

机构地区：[1]中国电子科技集团公司第20研究所通信部,陕西西安710068

出　　处：《电子科技》2015年第5期121-123,共3页Electronic Science and Technology

摘　　要：介绍了Turbo乘积码(TPC)的编译码原理,并对TPC码字结构进行了分析。在高斯信道下给出了子码为扩展汉明码(64,57,4)的TPC码的误码率性能,并对编译码器的模块设计进行说明,同时采用Altera公司的EP2S180芯片完成了方案验证。结果表明,在系统时钟为100 MHz的情况下,译码时延约为44μs,可较好地满足实时性需求。This paper introduces the principle of encoding and decoding on Turbo Product Code （TPC）, and analyzes the structure of TPC coding. Taking Sub-code （64, 57, 4） extended Hamming code in Gauss channel, this paper presents the performance of signal to noise ratio, and introduces the design of the module for TPC coding. Finally the Altera EP2S180 chip is used to verify the scheme. Results show that when the system clock is 100 MHz, the decoding delay is approximately 44 μs, which can meet the requirement of real-timeness.

关 键 词：TURBO乘积码 迭代译码 FPGA实现 

分 类 号：TN911.22[电子电信—通信与信息系统]