基于CPLD的LCD1602显示系统设计与实现  

Design and implementation of LCD1602 display system based on CPLD

作　　者：陈海峰[1] 丁丽丽[2] 

机构地区：[1]华南农业大学珠江学院,广东广州510900 [2]广州城建职业学院,广东广州510900

出　　处：《电子设计工程》2015年第10期182-185,共4页Electronic Design Engineering

摘　　要：为了提高LCD1602显示效果,增强抗扰能力,文章基于TOP2812开发板,依据LCD1602操作时序要求,在开发板CPLD部分实现了LCD1602显示系统的设计。文中对LCD1602时序进行了详细分析,并在Quartus II平台下采用Verilog HDL编写了test bench测试文件和驱动程序,经仿真和实际测试表明,显示效果较好,达到了设计要求。In order to improve the display effort and enhance anti-disturbance capability of LCD1602, in this paper, the LCD1602 display system was designed according to the timing diagram of LCD1602 based on CPLD which is part of TOP2812 development kits. The timing diagram of LCD1602 display system was analyzed in detail. The driver and test bench file were programmed in Verilog HDL on the platform of Quartus II. The simulation and actual test shown good display effort, which reached the design requirements.

关 键 词：CPLD LCD1602 显示系统 时序 VERILOG HDL 

分 类 号：TN46[电子电信—微电子学与固体电子学]