一种3D图形背面消隐算法及其硬件加速实现  

A 3D Graphics Backface Culling Algorithm and its Hardware Accelerating Implementation

作　　者：田泽[1] 杜斐[1] 张骏[1] 

机构地区：[1]中航工业西安航空计算技术研究所航空微电子技术研究室,西安710068

出　　处：《小型微型计算机系统》2015年第6期1403-1408,共6页Journal of Chinese Computer Systems

摘　　要：消隐操作在GPU中承担着设置三角形面的正面和反面,以及剔除特定面的任务,能够减少3D引擎对隐藏面的计算量,对提升GPU图形处理性能起着关键性的作用.本文推导了背面消隐图形算法,根据算法的推导结果,提出了一种背面消隐单元(BCU)结构,并描述了其中各模块功能及工作流程;针对BCU中核心计算单元提出了三种不同的硬件加速实现方案.采用Xilinx的ISE工具进行综合,并在Xilinx Vertex6 XC6VLX760 FPGA上进行原型验证,电路工作频率可以达到198MHz.分别从逻辑资源占用、工作频率、时钟周期数三个维度评估了三种硬件实现方案的优缺点.结果表明,采用最小共享单元方案不仅减少图形处理器的硬件资源,且能提高消隐计算效率.在SMIC 65nm CMOS工艺下,采用Synopsys Design-Compiler对设计进行综合,电路工作频率达到341MHz,满足设计需求.Surface culling sets the pros and cons of triangles, and removes given surfaces as well in （3PU, which reduces the amount of computation for surface culling, and plays a key role for increasing the graphic processing performance. This paper deduces the back- face culling algorithm in detail,and then,proposes a kind of backface culling unit（BCU） structure. Modules functions and processing flow of BCU are descfipted,and further ,three kinds of computing core implementation shemes for BCU hardware accelerating are pro- posed. We verify and evaluate the three different BCU implements on Xilinx Vertex6 XC6VLX760 FPGA prototype from resource. frequency and computing period. As a result,the frequency of prototype is up to 198MHz,BCU functions are correct and minimum share unit scheme is optimum choice. In addition,we synthesize the BCU RTL under SMIC 65nm CMOS library by using Synopsys Design-Compiler. The frequency of BCU design is up to 341MHz, which meets the design requirements.

关 键 词：图形处理器 3D引擎 背面消隐 FPGA 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]