基于导航系统的低功耗全集成频率综合器设计  

Design of a Low Power and Fully Integrated Frequency Synthesizer for the GNSS Receiver

作　　者：卢东旭[1] 高博[1] 耿双利[1] 田国平[2] 谷江[1] 丁理想[1] 赵永瑞[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051 [2]专用集成电路重点实验室,石家庄050051

出　　处：《半导体技术》2015年第6期421-425,共5页Semiconductor Technology

摘　　要：针对双模卫星导航接收系统对集成度、功耗和面积的需求,研究了频率综合器的电路结构和频率规划,分析了频率综合器环路的参数设计,实现了片上集成环路滤波器,版图采用MIM和MOS电容堆叠的方式节省了面积,电容电阻采用了加权的方式,使环路带宽可调。采用高速TSPC结构的D触发器构成双模预分频器,降低了整体电路的功耗。利用基于0.18μm RF CMOS工艺实现了低功耗全集成的频率综合器,芯片面积0.88 mm2,功耗18.5 m W,相位噪声-94 d Bc/Hz@100 k Hz,杂散-68 d Bc。测试结果证明了该电路系统参数设计和结构改进是合理和有效的,各参数性能满足系统要求。According to the requirement of the integration and power and area of the dual-mode satellite navigation receiver, the circuit structure and frequency planning of the frequency synthesizer was researched. The parameter design of the frequency synthesizer loop was analyzed,and the on-chip loop filter was realized. Stacking the MIM and MOS capacitor was used to reduce the area of the chip. The resistor and capacitor were weighted to make the bandwidth adjustable. The dual-mode prescaler was made up of high speed TSPC D trigger in order to reduce the power consumption. The low power and fully integrated frequency synthesizer was implemented in a 0. 18 μm RF CMOS technology. It occupies an area of 0. 88 mm^2 and consumes 18. 5 m W. The phase noise and spur achieve- 94 d Bc / Hz at 100 k Hz and- 68 d Bc,respectively. The test results show that the improved design on the parameter and structure of frequency synthesizer is reasonable and effective. The requirement of the system is met for all the parameter performances.

关 键 词：频率综合器 低功耗 全集成 环路滤波器 预分频器 

分 类 号：TN432[电子电信—微电子学与固体电子学]