基于SRAM和STT-RAM的混合指令Cache设计  

. Design of hybrid instruction Cache based on SRAM and STT-RAM

作　　者：皇甫晓妍 樊晓桠[1] 黄小平[1] 

机构地区：[1]西北工业大学计算机学院,西安710129

出　　处：《计算机工程与应用》2015年第12期43-48,共6页Computer Engineering and Applications

基　　金：国家自然科学基金(No.60773223;No.61003037;No.60736012;No.61173047);西北工业大学基础研究基金(No.JC20110224;No.JC201212)

摘　　要：随着工艺尺寸减小,传统基于SRAM的片上Cache的漏电流功耗成指数增长,阻碍了片上Cache容量的增加。基于牺牲者Cache的原理,利用SRAM写速度快,STT-RAM的非易失性、高密度、极低漏电流功耗等特性设计了一种基于SRAM和STT-RAM的混合型指令Cache。通过实验证明,该混合型指令Cache与传统基于SRAM的指令Cache相比,在不增加指令Cache面积的情况下,增加了指令Cache容量,并显著提高了指令Cache的命中率。With the decrease of the grain size, the leakage power of traditional on-chip SRAM-based Cache increases expo-nentially, which hinders the increase of capacity of Cache on chip. As SRAM’s write speed is faster and STT-RAM is non-volatile, high density and very low leakage power, this paper designs a hybrid instruction Cache with SRAM and STT-RAM. The experimental results show that, compared with the SRAM-based instruction Cache, the hybrid instruction Cache increases capacity and significantly improves the hit rate without increasing the area.

关 键 词：自旋转移力矩随机存储器(STT-RAM) 指令CACHE 混合Cache 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]