最优正规基下并行乘法器的设计  

Parallel Multiplier Design based on optimal Normal Basis

作　　者：苏丹丹[1] 付萍 

机构地区：[1]罗定职业技术学院,广东罗定527200 [2]北京昌平区回龙观中学,北京102200

出　　处：《重庆工商大学学报（自然科学版）》2015年第8期14-18,共5页Journal of Chongqing Technology and Business University:Natural Science Edition

基　　金：国家自然科学基金资助项目(10990011)

摘　　要：利用简单的组合逻辑电路分别在Ⅰ型和Ⅱ型最优正规基上设计出了新的并行乘法器,其中Ⅰ型最优正规基并行乘法器所需异或门数为3n-4,与门数为n,Ⅱ型最优正规基并行乘法器所需异或门数为2n-2,与门数为n;与Sunar和Koc于2001年在Ⅱ型最优正规基上提出的并行正规基乘法器对照,此乘法器大大减少了所需要的门数,从而有效地降低了硬件消耗的资源.A new parallel multiplier is designed by simple combinational logic circuits based on type I optimal normal basis and type Ⅱ optimal normal basis respectively. For the type I optimal normal basis, the parallel multiplier needs 3n-4 XOR gates and n AND gates, for the type Ⅱ optimal normal basis, the parallel multiplierneeds 2n-2 XOR gates and n AND gates. Compared with the normal basis parallel multiplier based on type Ⅱ optimal normal basis proposed by Sunar and Koc in 2001, this multiplier greatly reduces required gates so as to effectively decrease the resources of consumption.

关 键 词：有限域 最优正规基 乘法器 门数 

分 类 号：O154.2[理学—数学]