面向60 GHz系统的多码率LDPC分层译码器的设计  

Multi-mode LDPC layered decoder architecture for 60 GHz system

作　　者：江鹏刚 金德鹏[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《电子技术应用》2015年第7期23-25,29,共4页Application of Electronic Technique

摘　　要：针对60 GHz通信系统中的IEEE 802.11ad标准,提出了一种双层同步迭代式多码率LDPC分层译码器的结构。利用码率越低LDPC校验矩阵越为稀疏的特点,将所有码率下的校验矩阵压缩到单一检验矩阵,以便支持LDPC多码率译码。同时,使用分层译码算法,有效减少迭代次数。基于推荐结构,在Vertex-6 FPGA上实现了支持IEEE 802.11ad标准的4种码率的LDPC译码器,LUTs资源使用量为34%,最高净吞吐率达到3.507 Gb/s。比较结果表明,推荐结构有着低复杂度、高吞吐率的特点。Simultaneous two-layer iteration architecture for multi-mode LDPC layered decoder is proposed for the IEEE 802.1lad standard in 60 GHz communications systems. Via utilizing the property that the check matrix becomes more sparse as the code rate decreases, the check matrixes of all code rates have been compressed into the unique one for supporting multi-mode LDPC decoding. Meanwhile, layered iterative decoding are employed to reduce the number of iteration efficiently. Based on the proposed architecture, a four-code-rate LDPC decoder for the IEEE 802.1lad standard is implemented on Vertex-6 FPGA with 34% LUTs resources and the maximum throughput of 3.507 Gb/s. Comparison results show that the proposed decoding architecture has the advantage of low complexity and high throughput.

关 键 词：LDPC译码器 60 GHZ 双层同步迭代 高吞吐率 

分 类 号：TN911[电子电信—通信与信息系统]