Verilog HDL语言中always敏感信号对比分析  

Contrastive analysis of always sensitive signals in Verilog HDL language

作　　者：张稳稳[1] 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《现代电子技术》2015年第15期32-34,38,共4页Modern Electronics Technique

基　　金：陕西省教育厅专项科研基金(2013JK0626);西安邮电大学青年教师科研基金资助项目(101-1215;101-0473)

摘　　要：为了高效地利用Verilog HDL语言中always行为建模语句设计集成电路,采用比较和举例论证的方法,总结出always语句中事件控制敏感信号对设计仿真的影响。always语句中敏感信号分为时钟边沿信号和电平信号,对于敏感信号为时钟边沿信号,仿真结果直观简单;但是对于敏感信号为电平信号,敏感信号必须是所有的输入和判断语句的信号,否则仿真结果不确定。To use always behavioral modeling statements in Verilog HDL language to design integrated circuits efficiently, the influence of event control sensitive signals in always statement on design simulation are summarized by using comparison and illustrating arguments. The sensitive signals in always statements are divided into clock edge signal and level signal. When sensi?tive signal is the former,the simulation results are intuitive and simply. When sensitive signal is the latter,the sensitive signal must be the signal of all input and judgment statements,otherwise the simulation results are uncertain.

关 键 词：VERILOG HDL always语句 敏感信号 时钟边沿信号 时钟电平信号 

分 类 号：TN911.634[电子电信—通信与信息系统] TP312[电子电信—信息与通信工程]