基于有载品质因数的低抖动时钟电路研究  

Research of a low jitter clock circuit based on loaded quality factor

作　　者：邱渡裕[1] 田书林[1] 谭峰[1] 曾浩[1] 

机构地区：[1]电子科技大学自动化工程学院,成都610054

出　　处：《仪器仪表学报》2015年第7期1584-1591,共8页Chinese Journal of Scientific Instrument

基　　金：国家自然科学基金(61301263);中央高校基本科研基金(A03008023801080;ZYGX2014J067)项目资助

摘　　要：抖动作为衡量时钟信号质量的重要指标,对电子系统的性能具有重要意义。数据采集系统要获得良好的信噪比,就必须要有高性能低抖动的时钟信号。本文应用相位噪声与抖动的关系,同时结合相位噪声Leeson模型,研究了时钟信号发生电路的抖动及相位噪声特性,分析了电路有载品质因数QL对抖动的影响,并给出了电路主要器件与抖动关系的显性表达式。以一种100 MHz低抖动时钟信号发生电路为例,进行了理论分析、仿真和实验验证,并将其应用到2.5 GHz采样时钟信号发生电路中进行了对比测试。结果表明,提高电路的有载品质因素QL可以明显改善其抖动及相位噪声特性。Jitter is an important specification quantifying the quality of a clock signal, which has great significance for an electronic system. To obtain good signal-to-noise ratio performance for data acquisition systems, the clock signals with low jitter performance are required. By using the relationship between phase noise and jitter, considering the Leeson model of phase noise, the jitter and phase noise characteristics of clock signal generating circuit are studied in this paper. The impacts of the loaded quality factor （QL） of the circuit on jitter are analyzed, and the explicit expression of the main component performance of the circuit vs. jitter is given as well. A 100 MHz low jitter clock signal generating circuit was taken as example, the theoretical analysis, simulation and experiment verification were conducted; and this method was applied to a 2.5 GHz sampling clock signal generating circuit, and comparison test was carried out. The simulation and experiment results show that the jitter and phase noise characteristics can be improved by increasing of the loaded quality factor QL of the circuit.

关 键 词：相位噪声 低抖动时钟 有载品质因数 

分 类 号：TN710[电子电信—电路与系统] TH7[机械工程—仪器科学与技术]