基于DDR2SDRAM乒乓双缓冲的高速数据收发系统设计  

High-Speed Data Transceiver System Based on DDR2 SDRAM Ping-Pong Double Buffering

作　　者：刘杰[1] 赛景波[1] 

机构地区：[1]北京工业大学电控学院,北京100022

出　　处：《电子器件》2015年第3期650-654,共5页Chinese Journal of Electron Devices

摘　　要：在高速数据收发系统设计中,首先需要解决的问题是实时数据的高速缓存,然而FPGA内部有限的存储资源无法满足海量数据缓存的要求。为了解决系统中海量数据的缓存问题,系统创新提出了一种基于DDR2 SDRAM的乒乓双缓冲设计方案。方案设计了两路基于DDR2 SDRAM的大容量异步FIFO,通过FPGA内部选择逻辑实现两条通路间的乒乓操作,从而实现数据的高速缓存。实验结果表明,基于DDR2 SDRAM的数据收发系统实现了每路512 Mbit的缓存空间和200 MHz的总线速率,解决了海量数据的高速缓存问题。In the high-speed data transceiver system design,the first problem to be solved is the real-time data cache,However,the limited memory resources of FPGA can not meet the requirements of massive data cache,To solve the problem of system cache huge amounts of data,the system proposed ping-pong double buffering innovative design based on the DDR2 SDRAM. Design of two-way high-capacity asynchronous FIFO based on DDR2 SDRAM,selection logic operations to achieve a ping-pong between the two paths through the FPGA to achieve the cached data. Experimental results show that the Data transceiver system based on DDR2 SDRAM realized every road 512 Mbit cache space and 200 MHz of the bus rate and solved the problem of the huge amounts of data cache.

关 键 词：高速数据收发 乒乓双缓冲 DDR2 SDRAM技术 异步FIFO 

分 类 号：TN919.6[电子电信—通信与信息系统]