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机构地区:[1]北京京东方显示技术有限公司,北京100176
出 处:《液晶与显示》2015年第4期616-620,共5页Chinese Journal of Liquid Crystals and Displays
摘 要:研究各膜层对灰化速率的影响,增强对灰化工艺的了解,为四次光刻工艺改善提供参考。采用探针台阶仪测量在相同灰化条件下不同膜层样品的灰化速率和有源层损失量,对结果进行机理分析和讨论。实验结果表明:有源层会降低灰化速率,源/漏金属层可以增大灰化速率,栅极金属层对灰化速率无影响。对于正常膜层结构的阵列基板,源/漏层图形密度越大,灰化速率越小,图形密度每增大1%,灰化速率下降14nm/min。有源层和源/漏金属层对灰化等离子体产生影响,从而影响灰化速率。In order to enhance understanding of photoresist ashing and give reference to 4mask process improvement,the effect of each film layer on photoresist ashing was researched.In the same ashing process condition,ashing rate of samples with different film layer was measured byα-step profiler,and the mechanism of test result was analysed.Experimental results indicate that a-Si can decrease ashing rate,SD metal can increase ashing rate,gate metal has no effect on the ashing rate.And for normal film structure TFT array substrate,the bigger SD pattern density is,the smaller ashing rate will be.If SD pattern density increased 1%,ashing rate would decreased 14nm/min.Because of influence on ashing plasma,a-Si and SD metal have an effect on ashing rate.
分 类 号:TN141.9[电子电信—物理电子学]
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