一种基于全差分积分器的时钟稳定电路设计  

Design of a Clock Stabilizer Based on Full Differential Integrator

作　　者：罗凯[1,2] 朱璨[2] 胡刚毅[2] 

机构地区：[1]重庆大学,重庆400044 [2]模拟集成电路重点实验室,重庆400060

出　　处：《微电子学》2015年第4期437-440,共4页Microelectronics

摘　　要：设计了一种用于超高速A/D转换器的时钟稳定电路。利用全差分连续时间积分器将差分时钟信号的占空比量化为电压信号,再通过跨导放大器产生控制电流来调整输出时钟的共模电平,达到调整输出时钟占空比的目的。电路采用0.18μm标准CMOS工艺进行设计,工作电压为1.8V,在2GHz的最高时钟频率下,将占空比为20%~80%的输入时钟信号调整为（50±1）%,输出时钟抖动小于132fs,具有抑制时钟抖动的能力。A clock stabilizer was designed for ultra-speed A/D converter. Differential clock signals were converted to voltage signals with full differential continuous-time integrator, then the control currents generated by transconductance amplifier were used to adjust the output clocks common level to regulate the clock duty cycle. Fabricated in 0. 18 μm process, the circuit could tune the range of input clock duty cycle from 20%-80% to （50± 1）% at a supply voltage of 1.8 V and a maximum clock frequency of 2 GHz. The output clock jitter was less than 132 fs. The proposed circuit could suppress the clock iitter.

关 键 词：时钟稳定电路 全差分连续时间积分器 占空比调整 

分 类 号：TN432[电子电信—微电子学与固体电子学]