高性能双栅复合介质ZnO薄膜晶体管的模拟  

Analog of High-performance Double-gate Multiple-layer ZnO Thin-film Transistors

作　　者：王昭[1] 姚阳[1] 钟传杰[1] 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122

出　　处：《固体电子学研究与进展》2015年第2期115-119,共5页Research & Progress of SSE

基　　金：国家自然基金资助项目(60776056)

摘　　要：提出ZnO薄膜晶体管的一种新型结构——双栅复合介质结构,并利用ATLAS软件对双栅复合介质结构与双栅单介质结构进行仿真。对比分析结果表明,采用复合介质材料可以明显提高器件的电学特性,在相同偏置条件下,双栅复合介质结构饱和电流为5.5×10-5 A,阈值电压为5.83V,亚阈值斜率为0.128V/dec,开关电流比为109;双栅单介质结构相应值分别为1.3×10-7 A、15.5V、0.297V/dec和108。通过晶界势垒高度随VGS变化分析了新型结构阈值电压降低的物理机制。A novel structure of ZnO thin-film transistor with double-gate and multiple-layer insulator was proposed and simulated with ATLAS software.The new thin-film transistor with multiple-layer insulator has better electrical characteristics,compared with the conventional double-gate one-layer ZnO TFT.Under the same bias condition,double-gate multiple-layer TFT has a saturation current of 5.5×10^-5 A,threshold voltage of 5.83 V,subthreshold slope of0.128V/dec,on-off current ratio of 109;while the four subjects of double-gate one-layer TFT are1.3×10^-7 A,15.50 V,0.297 V/dec,108,respectively.The barrier height variation of grain boundary with VGSchange was analyzed to make clear the physical mechanism of threshold voltage decrease of the novel structure.

关 键 词：氧化锌薄膜晶体管 双栅复合介质 晶粒间界 势垒高度 

分 类 号：TN321.5[电子电信—物理电子学] TN325.3