图形处理器剪裁加速器的设计与实现  

Design and Implementation of Clipping Accelerator in GPU

作　　者：田泽[1] 邓惠子[1] 张骏[1] 许宏杰[1] 黎小玉[1] 

机构地区：[1]中国航空工业西安航空计算技术研究所,陕西西安710068

出　　处：《微电子学与计算机》2015年第9期105-108,113,共5页Microelectronics & Computer

摘　　要：平面剪裁和视景体剪裁是图形处理器中3D引擎的核心功能,而在进行复杂场景绘制时,剪裁操作容易成为整个3D引擎的瓶颈.对此提出一种优化的剪裁加速器结构,并完成了剪裁加速器单元的设计与实现.在Xilinx Vertex6XC6VLX760FPGA上进行原型验证,电路工作频率可以达到196 MHz,测试功能正确.在SMIC 65nm CMOS工艺下,电路工作频率达到315 MHz,满足设计需求.Plane clipping and frustum clipping is a key function in GPU 3D engine.But unfortunately,the clipping module is more easy to become the bottleneck of whole 3D engine.This paper proposes a optimized clipping accelerator（CA）architecture,and completes the design and implementation of clipping accelerator.Further,on Xilinx Vertex6 XC6VLX760 FPGA for prototype verification,the frequency of prototype is up to 1 96 MHz and the functions are correct.In addition,we synthesize the RTL under SMIC 65 nm CMOS library,the frequency of design is up to 31 5 MHz,which meets the design requirements.

关 键 词：图形处理器 平面剪裁 视景体剪裁 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]