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机构地区:[1]桂林电子科技大学电子工程与自动化学院,桂林541004
出 处:《国外电子测量技术》2015年第8期29-33,共5页Foreign Electronic Measurement Technology
基 金:国家自然科学基金(61102012);广西自动检测技术与仪器重点实验室主任基金(YQ14105)项目
摘 要:测试功耗、测试时间是SoC测试优化中的两个测试目标,它们之间存在相互影响的关系。在多目标优化过程中,进化算法对于解决多目标优化问题拥有比较好的优化效果,因此各种进化算法被广泛地应用于SoC测试多目标优化的研究中。对SoC测试时间、测试功耗这两个测试目标建立联合优化模型,分析了NSGA-Ⅱ算法与SPEA-Ⅱ算法的特点,并对改进型强度Pareto进化算法(SPEA-Ⅱ)进行研究,进而将SPEA-Ⅱ算法用于上述所建立模型的求解。使用ITC’02标准电路中p93791电路和d695电路对上述方法进行实验验证,实验数据表明上述方法可以求得该联合优化模型的一组最优解;并且针对p93791电路,在与NSGA-Ⅱ算法的实验数据比较中,得到了更好的优化结果。证明了SPEA-Ⅱ算法对SoC测试结构优化方面具有良好的适用性和可行性。In the system chip SoC test optimization,test power and test time are the two test target,they exist interaction relations.In the process of multi-objective optimization,evolutionary algorithm for solving multi-objective optimization problem has good effect,so various evolutionary algorithms are widely used in SoC test in the study of multi-objective optimization.In the absence of SoC test time or test power consumption as the constraint conditions under the premise of the SoC test time and test power joint optimization model of the these two goals.And the improved Strength Pareto Evolutionary Algorithm(SPEA-II)is studied,which will SPEA-II Algorithm used for the solution of the model established.Use the ITC'02standard p93791 circuit and d695 in the circuit of the above methods to experimental verification,the results show that the method can equilibrium solution is provided for the established joint optimization model.And in view of the p93791 circuit,in the experimental data with the NSGA-II algorithm comparison,better optimization results were obtained.To prove to SPEA-II SoC test architecture optimization has good applicability and effectiveness.
关 键 词:SPEA-Ⅱ算法 SOC测试 测试时间 测试功耗
分 类 号:TP302[自动化与计算机技术—计算机系统结构]
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