低功耗DDR高速信号的封装布线方案设计及信号完整性分析  

Packaging wiring scheme design and integrality analysis of LPDDR high-speed signal

作　　者：秦征[1,2] 尚文亚 于大全[2] 

机构地区：[1]中国科学院大学,北京100049 [2]中国科学院微电子研究所,北京100029

出　　处：《现代电子技术》2015年第19期135-139,共5页Modern Electronics Technique

基　　金：国家科技重大专项资助项目:极大规模集成电路制造装备及成套工艺(2014ZX02501)

摘　　要：不同于印制电路板的制作工艺,芯片封装基板的走线更细,线间距更窄。狭小的布线空间使传输线效应更为明显,而且封装设计的好坏直接影响芯片是否可以正常工作,同时芯片成本的控制要求布线层尽量要最少。这些问题使得高速信号布线面临严峻的挑战。在国家科技重大专项的资助下,使用全波电磁场仿真工具进行建模分析,研究了布线中线宽、线间距和参考地对信号传输质量和信号间串扰的影响,并且基于一款低功耗DDR高速芯片的双层封装布线设计,在实际设计方案中对分析结果进行了仿真验证,最终得到了一种高质量、低成本封装基板高速布线方案,速率达到1 333 Mb/s。Compared with manufacture technique of printed circuit board,thinner wirings and more narrow wire spacing on the chip package substrate are needed. The narrow wiring space makes the transmission line effect more obvious. The packaging design impacts chip performance directly. The least wiring layers are needed for cost control of chip,which make the wiring of high？speed signal be faced with crucial challenge. This work is supported by the“National Science and Technology Major Proj？ect”. Modeling analysis is conducted with the full？wave electromagnetic field simulation tools to research the influences of wires′central line width,wire spacing and reference ground on signal transmission quality and signal crosstalk. Based on the double？layer packaging wiring design of a high？speed LPDDR chip,the analysis results were verified by simulation in actual design scheme. A high？speed wiring scheme of packaging substrate with high quality and low cost was obtained,whose rate reaches 1 333 Mb/s.

关 键 词：DDR 高速信号 封装布线 信号串扰影响 电路设计 

分 类 号：TN702[电子电信—电路与系统]