FPGA的高性能暗原色先验算法设计  

High-performance dark channel prior algorithm design of FPGA

作　　者：蒋守欢 汪荣贵[1] 王晶[1] 张冬梅[1] 李想[1] 

机构地区：[1]合肥工业大学计算机与信息学院,合肥230009

出　　处：《计算机工程与应用》2015年第19期158-163,共6页Computer Engineering and Applications

基　　金：国家自然科学基金(No.61075032);安徽省自然科学基金(No.1408085QF117)

摘　　要：对暗原色先验算法中引导滤波器进行改进,提出了一种快速计算像素模板均值的方法,并设计了这种改进方法的电路结构。模板均值是通过存储局部窗口第一列和最后一列的和,加上/减去其相应列中某个像素点的值得到,这种计算方法不仅能够在不改变滤波效果的前提下使计算复杂度降低到常数级,而且更符合FPGA的并行流水设计。实验结果表明,在Altera公司Cyclone II系列的EP2C70的FPGA开发板上的逻辑和内存的使用量分别占7.9%和35%,低端FPGA能够满足需求,每秒可处理100帧1 024′1 024的图像,实时性完全达到要求。Based on dark channel prior algorithm to improve guide filter, a fast method of calculating the mean pixel tem- plate is proposed, and the circuit structure of the improved method is designed. The mean template is achieved by means of storing the sum of the first and the last column of local window, and then plus/minus the corresponding column in the value of a pixel. Under the premise of unchanging the filter effect, this calculation method can effectively reduce the com- putational complexity to constant level and more fit the parallel flow design of FPGA. Experimental results show that the series EP2C70 FPGA development board of Altera Corporation CycloneⅡ, its usage of logic and memory is 7.9% and 35% respectively, the low-end FPGA can satisfy the demands, 100 frames 1 024 × 1 024 images can be handled in every second, and real-time fully meet the requirements.

关 键 词：暗原色先验 引导滤波器 现场可编程门阵列 

分 类 号：TN911.72[电子电信—通信与信息系统]