一种含LDE效应的深亚微米电路设计流程  

LDE-Aware Circuit Design Flow for Deep Sub-Micro Process Nodes

作　　者：冯光涛[1] 陈先敏 杨家奇 

机构地区：[1]中芯国际集成电路制造有限公司,上海201203

出　　处：《微电子学》2015年第5期670-672,共3页Microelectronics

基　　金：国家科技重大专项02专项资助项目(2013ZX02301-001)

摘　　要：介绍了一种包含LDE效应的深亚微米电路设计流程。分析了100nm以下工艺节点LDE效应对器件的影响,以及传统集成电路设计方法的局限性。在此基础上,提出了包含LDE效应的电路设计方法,并通过中芯国际先进工艺节点的模拟电路设计实例进行了验证。结果表明,在亚100nm工艺节点,尤其在40/45nm及以下节点,LDE效应的影响已不可忽略,需要采用含LDE效应的电路设计流程。The LDE-aware circuit design flow was presented to address the new challenges at sub-100 nm CMOS process nodes. The LDE effect and its impact upon the circuit design having been briefed, the limitation of the traditional circuit design flow was explored, and then the LDE-aware circuit design flow was proposed, which was adopted in the analog integrated circuit designs for the advanced process nodes offered by SMIC. The results revealed that at the 100 nm node, especially at the 40/45 nm and below nodes, the impacts of the LDE effect could not be neglected, and the LDE-aware design flow was necessary.

关 键 词：LDE效应 深亚微米 电路设计流程 模拟集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]