一种高性能数字输出端口电路设计  

A Design for High-performance Digital Output I/O Circuit

作　　者：陈迪平[1] 陈思园[1] 曾健平[1] 

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082

出　　处：《湖南大学学报（自然科学版）》2015年第10期78-82,共5页Journal of Hunan University:Natural Sciences

基　　金：湖南省工业支撑计划项目(2013GK3019);湖南省科技计划资助项目(2014GK3148)

摘　　要：传统多电源系统数字输出端口存在上拉、下拉竞争和上升沿与下降沿的严重不对称等问题,使得延时功耗积很大;而电压波动和误触发导致系统SSN噪声较大.针对这2个问题,提出一种采用快速低转高电平转换电路结构和抗地弹效应输出电路的新型输出端口电路结构,在smic18mmrf工艺下流片.测试结果表明,电平转换单元功耗延时积较传统结构减小5%~15%,SSN噪声幅度减少30%以上,有效提高了输出端口电路性能.. In the digital output port of the traditional multi-power system, there are pull-up-drop-down competition and serious asymmetry between positive edge and negative edge, which results in a large delay- power product, while the large voltage fluctuation and spurious triggering result in a high SSN noise. To deal with these problems, this paper proposed a novel output circuit architecture, which employs a quick voltage level transform circuit to reduce the delay-power product and a resistance of ground bounce output structure to reduce the SSN noise. The output circuit was fabricated by SMIC18mmrf process, and the test shows that the delay-power consumption product is reduced by 5%- 15% and SNN noise amplitude is low- ered by 30 %, compared with the traditional circuit, which indicates the high performance of the novel output circuit.

关 键 词：噪声减少 转换电路 电平转换 同步开关噪声(SSN) 延时功耗积 地弹效应 功耗 阈值电压 

分 类 号：TN402[电子电信—微电子学与固体电子学]