高速深流水线浮点加法单元的设计  

The design of high-speed deep pipeline floating-point adder unit

作　　者：张明[1,2] 郑莉平[1] 余宁梅[1] 

机构地区：[1]西安理工大学自动化与信息工程学院,陕西西安710048 [2]中国航天科技集团公司第九研究院第七七一研究所,陕西西安710119

出　　处：《微型机与应用》2015年第20期15-17,共3页Microcomputer & Its Applications

摘　　要：在X87执行环境下,采用基于Two-Path算法的并行深度流水线优化算法,设计了一种能够实现符合IEEE-754标准的单精度、双精度和扩展双精度及整型数据且舍入模式可控的高速浮点加法器。采用并行深度流水设计,经验证,功能满足设计要求,使用TSMC 65 nm工艺库进行综合,其工作频率可达900 MHz。The paper describes a high-speed floating point adder design, which achieves compliance with IEEE-754 standard single-precision, double-precision, extended-double-precision and integer data with rounding mode controlled, working under X87 execution environment. The design is based on Two-Path algorithm with parallel pipeline depth optimization algorithm. The paper puts forward a deep parallel pipeline design. After verification the function meets the design requirements, using TSMC 65 nm technology library, whose operating frequency is up to 900 MHz.

关 键 词：浮点加法器 IEEE-754 Two-Path算法 并行流水线 

分 类 号：TP332.1[自动化与计算机技术—计算机系统结构]