基于AD9517-1的高速时钟系统稳定性设计与信号完整性分析  

Stability design of a high speed clock system based on AD9517-1 and signal integrity analysis

作　　者：俞一超 吴宪顺[1] 庄晴光[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《天津理工大学学报》2015年第5期16-20,共5页Journal of Tianjin University of Technology

摘　　要：本文以一个14位,转换速率250 MSPS的模数转换器(ADC)为信号终端,提出了一种提高高速ADC时钟电路稳定性的解决方案.方案使用AD9517-1作为时钟分配芯片,为芯片设计了一款中心频率250 MHz,相位噪声-98.7d Bc/Hz的三阶环路滤波器.信号输出性噪比(SNR)70.12 d B,时钟抖动282 fs rms,带宽496 fs rms.通过分析时钟信号的过冲和反射现象,对输出信号进行了基于低温共烧陶瓷工艺(LTCC)的微带线复数阻抗匹配和仿真.This paper puts forward a high-speed analog-digital converter（ADC）clock circuit stability solutions based on a 14 bit,conversion rate at 250 MSPS ADC for signal terminal. Solution was used AD9517-1 as the clock divider. A third order loop filter was designed：Center frequency at 250 MHZ,phase noise-98.7 d Bc/Hz. Output signal noise ratio（SNR）70.12 d B,clock jitter 282 fs rms,bandwidth 496 fs rms. With the analysis of the overshoot of the clock signal and reflection phenomenon,microstrip line complex impedance matching simulation was given out based on low temperature co-firing ce-ramic technology（LTCC）.

关 键 词：时钟系统 高速电路 环路滤波器 微带线 阻抗匹配 

分 类 号：TN830.3[电子电信—信息与通信工程]