一种超低静态功耗LDO的设计  

An ultra-low quiescent current LDO

作　　者：刘博[1,2] 刘欣[3] 樊晓华[3] 杨骏[1,3] 张海英[3] 

机构地区：[1]南京中科微电子有限公司,江苏南京210042 [2]中国科学院大学,北京100049 [3]中国科学院微电子研究所,北京100029

出　　处：《电子技术应用》2015年第11期51-53,57,共4页Application of Electronic Technique

摘　　要：介绍了一种采用0.35μm CMOS工艺制作的LDO电路。电路采用工作在亚阈值区的跨导放大器使得电路工作在超低静态电流下,因此实现了超低静态功耗和高效率性能。整个电路所占面积约为0.8 mm2,在典型工作状态下电路总的静态电流约为500 n A,最大负载电流为150 m A。电路输入电压为3.3 V^5 V,输出电压为3 V。A low voltage low dropout regulator（LDO） is presented, which utilizes the proposed operational transconductance amplifier working in the subthreshold region to achieve ultra-low quiescent current, thus contributing to a low power consumption and a high efficiency. The proposed LDO is designed in a 0.35μm standard CMOS process, and the whole circuit occupies an area of 0.8 mm2, dissipating a quiescent current flow of 500 nA at typical working condition as well as delivering a largest current of 150 mA at full-load condition. The circuit is operable with the input voltage ranging from 3.3 V to 5 V, and the output voltage is 3 V.

关 键 词：LDO 超低静态功耗 跨导放大器 亚阈值 

分 类 号：TN432[电子电信—微电子学与固体电子学]