利用FPGA的IRIG-B码解码新方法  

A Novel Method of IRIG-B Decoder using FPGA

作　　者：秦娟[1] 徐月超 李琨[1] 

机构地区：[1]天津理工大学电子信息工程学院薄膜电子与通信器件重点实验室,天津300384

出　　处：《信号处理》2015年第12期1654-1657,共4页Journal of Signal Processing

基　　金：天津市科技成果转化项目(12ZCZDJC35500);天津市自然科学基金青年项目(13JCQNJC01300)资助

摘　　要：时间统一是现代航天和常规武器试验靶场的重要组成部分,本文提出了一种兼顾准确度和实时性的解码方法。该方法根据IRIG-B码的信号特征,设计了一种新的解码算法。根据脉冲宽度调制波形在寄存器中预设数值,将IRIG-B码和移位寄存器进行移位比对,识别码字以及解析时间信息;根据起始标志信息特点预设111111110011111111移位比对,触发秒脉冲并输出1 pps信号。使用Model Sim进行了仿真,并下载到在Xilinx的XC3S1000芯片上实现。实验测试结果,秒脉冲触发误差小于20 ns。本文提出的方法具有精度高、简单实用、效率高等优点,具有较强的抗干扰性。Time system plays an important role in modern space flight and normal weapon test shooting range. A novel decoder method is proposed that the real-time property of decoder is improved by FPGA and the precision is high. According to the signal feature of IRIG-B code,a new decoding scheme is put forward. The values in registers are preset by pulsewidth modulation waveform and the IRIG-B code and shift register is compared. Then the code is identification and the time information can be resolved. The second pulse signal is triggered by shifting comparison with 111111110011111111 according to the starting marks information characteristics and 1pps signal is produced. It is simulated with Model Sim and is implemented on Xilinx＇ s XC3S1000 chips. The trigger error of a single second pulse signal is less than 20 ns. Experiments prove that the proposed method has high precision,simple and practical,high efficiency,improve the decoding accuracy and strong anti-jamming.

关 键 词：时间统一 IRIG-B码 FPGA设计 解码 

分 类 号：TP317[自动化与计算机技术—计算机软件与理论]