高速并行处理模式下同步时序研究  

Study on Synchronous Clock Signal Transmission of High-speed Parallel Processing Source Mode

作　　者：查环 

机构地区：[1]海装装备采购中心,北京100097

出　　处：《液压与气动》2015年第11期131-134,共4页Chinese Hydraulics & Pneumatics

摘　　要：总结了高速时钟电路时序分析及计算方法,并且对SDRAM在源同步工作方式下的总线时序计算做出了全面的介绍。通过对实际电路设计的分析得出了具有参考价值的结论,并对高速电路的PCB布局给出了分析。This paper described the analysis and calculate methods of high-speed clock signal transmission, and also described in details the calculate of bus sequence of SDRAM which working on source synchronous mode. It point some valuable conclusions from the analysis of the case, and also give some reasonable advices about principle of high-speed circuit PCB layout.

关 键 词：高速时钟电路 源同步工作方式 裕量 SDRAM 

分 类 号：TH137[机械工程—机械制造及自动化]