超深亚微米工艺下基于热量分区的SoC热感知测试调度方法  

Thermal-aware test scheduling of SoC based on thermal partition in ultra deep submicron technology

作　　者：焦铬[1] 李浪[1] 刘辉[1] 邹祎[1] 

机构地区：[1]衡阳师范学院计算机科学与技术学院,湖南衡阳421002

出　　处：《计算机应用研究》2015年第12期3682-3684,3696,共4页Application Research of Computers

基　　金：湖南省科技厅科技计划资助项目(2013FJ3077);湖南省教育厅资助科研项目(12C1084);衡阳市科技计划资助项目(2012KJ31);湖南省"十二五"重点建设学科资助项目(湘教发[2011]76号)

摘　　要：在超深亚微米时代,功耗不但直接影响芯片的封装测试成本,而且过高的功耗将导致芯片热量的增加,影响着芯片的可靠性,为了保证芯片测试的热安全,基于热感知的测试调度方法越来越受到重视。综合考虑超深亚微米工艺下,漏电功耗、空闲芯核唤醒功耗、分区开销和热量等约束条件对So C芯片测试的影响,利用叠加原理迅速而准确地计算功耗和热量分布,提出了一种基于热量分区的热感知测试调度方法,避免出现芯片局部过热的现象。在ITC’02基准电路上的实验结果表明,该方法在保证芯片热安全的同时,能有效地减少测试时间。In the ultra deep submicron era, power consumption will not only directly affect the chip packaging and testing costs, and excessive consumption will lead to increased temperature of chips, directly determines the reliability of the chip, in order to ensure security chip thermal testing, based on the thermal sensing the test scheduling method gets more attention by researchers. Considering the ultra-deep sub-micron technology, the infIuence of leakage power, wake-up power, partition overhead and thermal constraints on the SoC chip testing, using the superposition principle to quickly and accurately calculate the power consumption and heat distribution, this paper proposed a thermal heat partition scheduling method based on percep- tion test, to avoid the chip from local overheating. Experimental results on ITC＇02 benchmark circuits show that the method of ensuring chip thermal security, can effectively reduce the test time.

关 键 词：超深亚微米 片上系统 热量分区 热感知测试调度 

分 类 号：TN407[电子电信—微电子学与固体电子学]