基于伯努利分布的逻辑电路可靠度计算方法  

Reliability Calculation Method of Logical Circuit Based on Bernoulli Distribution

作　　者：蔡烁[1,2] 邝继顺[1] 刘铁桥[3] 凌纯清[1] 尤志强[1] 

机构地区：[1]湖南大学信息科学与工程学院,湖南长沙410082 [2]长沙理工大学计算机与通信工程学院,湖南长沙410114 [3]杭州电子科技大学管理学院,浙江杭州310018

出　　处：《电子学报》2015年第11期2292-2297,共6页Acta Electronica Sinica

基　　金：国家自然科学基金(No.61303042;No.60773207;No.61472123);湖南省教育厅科研基金(No.14C0028)

摘　　要：在深亚微米及纳米级集成电路设计过程中,电路的可靠性评估是非常重要的一个环节.本文提出了一种利用概率统计模型计算逻辑电路可靠度的方法,将电路中的每个逻辑门是否正常输出看作一次随机事件,则发生故障的逻辑门数为某个特定值的概率服从伯努利分布;再利用实验统计单个逻辑门出错时电路的逻辑屏蔽特性,根据此方法计算出ISCAS’85和ISCAS’89基准电路可靠度的一个特定范围.理论分析和实验结果表明所提方法是准确和有效的.Reliability estimation of logical circuit is becoming an important feature in the design process of deep submicron and nanoscale systems. In this paper,a reliability calculation method of logical circuit based on probability statistical model is proposed. Based on this model,the correctness of every logic gate is regarded as random event and obeying Bernoulli distribution.M eanwhile,simulation experimental results are given to analyze the logical masking properties of the circuit when only one gate set as faulty. To validate the proposed methodology we have studied the reliability range of ISCAS＇85 and ISCAS ＇89benchmark circuits. Theoretical analysis and experimental results showour method is accurate and efficient.

关 键 词：软错误 可靠度 概率统计模型 逻辑屏蔽 伯努利分布 

分 类 号：TN406[电子电信—微电子学与固体电子学]