基于FPGA的硬件排序系统设计  

Hardware sorting system design based on FPGA

作　　者：胡二猛[1] 钱承山[1] 张永宏[1] 许强[1] 

机构地区：[1]南京信息工程大学信息与控制学院,江苏南京210044

出　　处：《电子技术应用》2015年第12期39-41,共3页Application of Electronic Technique

摘　　要：针对软件排序速度慢、排序数据量小以及占用CPU资源多等问题,设计了一种基于FPGA的硬件排序系统。排序过程采用DMA工作方式,不占用CPU资源;数据传输采用SISO(串行输入/串行输出)方式,减少FPGA内部布线资源,增强排序系统可靠性。利用Modelsim仿真工具对硬件排序系统进行仿真验证,仿真结果表明,硬件排序系统可以有效提高排序效率以及降低CPU使用率。Aiming at the problems of software sorting, such as slow speed, small sorting data volume and large occupancy of CPU resource, a hardware sorting system based on FPGA （Field Programmable Gate Array） is designed. This system has the following characters： sorting process adopts DMA （Direct Memory Access）, without occupying the CPU resource; data transmission adopts SISO （Serial Input Serial Output）, lessening the internal wiring resources of FPGA and enhancing the system reliability. The sorting hard- ware model is verified through Modelsim simulation tool. The simulation result shows that the hardware sorting system can effectively improve the sorting efficiency and reduce CPU usage rate.

关 键 词：FPGA 硬件排序 DMA SISO 提高排序效率 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]