数字下变频中抽取滤波器的设计及FPGA实现  

Design and FPGA implementation of decimation filter in DDC

作　　者：周云[1] 冯全源[1] 

机构地区：[1]西南交通大学微电子研究所

出　　处：《电子技术应用》2015年第12期45-47,50,共4页Application of Electronic Technique

基　　金：国家自然科学基金项目(61271090);四川省科技支撑计划项目(2015GZ0103)

摘　　要：针对软件无线电接收机数字下变频中高速数字信号的降采样需求,利用半带滤波器及级联积分梳状滤波器,设计了一种半带滤波器前置的多级抽取滤波器架构。通过Simulink搭建系统模型验证之后,利用Xilinx ISE 12.3在Xilinx xc5vsx95t-2ff1136 FPGA上实现了一种下采样率为64的抽取滤波器。Modelsim仿真结果表明,该抽取滤波器设计是有效的,达到了设计指标。A structure of multistage decimation filter with half-band filter preposed was designed taking advantages of half-band fil- ter（HBF） and cascaded integrator-comb filter, for satisfying down sampling demands of high-speed digital signal in digital down conversion of software defined radio receivers. A decimation filter with down sampling ratio of 64 was implemented on Xilinx xc5vsx95t-2ff1136 FPGA using Xilinx design suite 12.3 after verifying by building system model utilizing Simulink. Simulation re- suits of Modelsim SE 6.5 proved that the design was efficient and that the designed goals were achieved.

关 键 词：降采样 多级抽取滤波器 半带滤波器 积分梳状滤波器 SIMULINK模型 FPGA实现 

分 类 号：TN911.72[电子电信—通信与信息系统]