面向OpenGL的图形加速器设计与实现  

Design and implementation of the graphics accelerator oriented to OpenGL

作　　者：邓军勇[1] 李涛[1] 蒋林[1] 韩俊刚[1] 沈绪榜[2] 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安电子科技大学微电子学院,陕西西安710071

出　　处：《西安电子科技大学学报》2015年第6期124-130,共7页Journal of Xidian University

基　　金：国家自然科学基金重点资助项目(61136002);国家自然科学基金资助项目(61272120);陕西省自然科学基金资助项目(2013JC2-32;2015JM6326);西安邮电大学青年教师科研基金资助项目(ZL2014-21)

摘　　要：为了探索图形处理器的自主开发,设计了一款基于经典流水线结构、支持OpenGL核心函数的图形加速器,并对其中几何变换、投影变换和视窗变换的关键操作——矩阵运算、图元装配以及光栅化等单元进行了优化设计以提高效率,支持Gouraud着色、光照、全屏抗锯齿、纹理贴图等效果.为保证电路功能的正确性,构建了基于C/C++的软件仿真平台和基于SystemVerilog的硬件仿真平台,并采用Altera公司的EP2C70F896C6搭建原型系统,电路规模约占FPGA总资源的83%,工作频率可达100MHz.经过大量实例测试,图形加速器具备基本的图形渲染能力.In order to explore the self-development of the graphics processing unit, this paper presents the design of a graphics accelerator which utilizes the classical pipelined structure and supports OpenGL primary commands. The matrix computational unit, which is the critical operation of geometric transformation, projection transformation and viewport transformation, primitive assembly unit and rasterization unit have been optimized to improve the efficiency. The accelerator realizes the rendering effects of Gouraud shading, lighting, full-screen anti-aliasing and texture mapping. In order to verify the circuit, the software and hardware simulation workbench based on C/C＋ q- and SystemVerilog respectively have been established. The prototype system is implemented on EP2C70F896C6 of Altera which takes up to 83% of the FPGA resource, with the speed being up to 100MHz. The test results of plenty of rendering applications show that the accelerator possesses the capability of graphics rendering.

关 键 词：图形加速器 矩阵运算 图元装配 全屏抗锯齿 原型系统 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]