基于FPGA的高精度多通道时间数字转换器设计  

Design of a High Resolution and Multichannel TDC Based on FPGA

作　　者：王巍[1] 董永孟 李捷[1] 熊拼搏 周浩[1] 杨正琳[1] 王冠宇[1] 袁军[1] 周玉涛 

机构地区：[1]重庆邮电大学光电工程学院,重庆400065 [2]重庆莲芯电子科技有限公司,重庆400065

出　　处：《微电子学》2015年第6期698-701,705,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61404019)

摘　　要：采用Xilinx Virtex-5FPGA芯片,实现了一种高精度、多通道时间数字转换器的设计。每个通道配有一条抽头延迟线,每条延迟线由64个快速超前进位链(CARRY4)组成。布线后,延迟线成链状结构紧密排列,有效消除了布线路径带来的误差,降低了积分非线性和微分非线性误差。仿真结果表明,设计的时间数字转换器的最低有效位约为26.35ps,有效精度约为14ps,INL小于4.3LSB,DNL在-0.8LSB^2.4LSB范围内。A high resolution and multichannel time-to-digital converter was designed with Xilinx Virtex-5 FPGA. Each channel was equipped with a tapped delay line, and 64 CARRY4 units were contained in each delay line. After place and route, the delay elements connected to be a chain structure, which greatly eliminated the errors that caused by the routing path, and resulted in very small differential nonlinearity and integral nonlinearity. The simulation results showed that the TDC＇s least significant bit was about 26.35 ps, the effective accuracy （RMS） was about 14 ps. INL was smaller than 4.3 LSB, and DNL was at the range of -0.8 LSB and 2.4 LSB.

关 键 词：FPGA 时间数字转换器 抽头延迟线 快速超前进位链 

分 类 号：TN79[电子电信—电路与系统]