一种改进的2位全并行A/D转换器  

An Improved 2 Bit Flash A/D Converter

作　　者：史海峰[1] 黄海生[1] 

机构地区：[1]西安邮电大学电子工程学院,西安710121

出　　处：《微电子学》2015年第6期702-705,共4页Microelectronics

基　　金：陕西省科技统筹创新工程计划项目(2012KTCQ01-06);陕西省教育厅产业化培育项目(2013JC10);国家科技重大专项资助项目(2013ZX03001010-003);西安邮电大学青年教师科研基金资助项目(101-0490)

摘　　要：基于0.18μm CMOS工艺,设计了一种改进的2位全并行A/D转换器。ADC的输入信号采用差分输入形式,差模输入信号经过源跟随器后直接进入比较器,去除了参考电压所需的电阻网络和模拟采样保持电路模块。在编码电路之后加入一个数字采样保持器,实现了时钟对量化信号的采集和数据同步对齐。仿真结果表明,在1.8V工作电压、25μA和15μA偏置电流下,可以对频率为4 MHz,摆幅为100mV的两路差模信号进行量化,整体功耗小于0.5mW。An improved 2 bit flash analog-to-digital converter（ADC） was designed with 0. 18μm CMOS process. The input signals of the proposed ADC were differential, and they were directly entered into the comparator after the source follower. The resistor network and analog sample/hold circuit in the proposed ADC architecture were removed, and a digital sample/hold circuit was added behind the encoding circuit in order to realize the acquisition of quantizing signals by clock and data synchronization. The simulation results showed that the proposed ADC could quantify the two-way differential mode signal of 4 MHz frequency and 100 mV swing at a supply voltage of 1.8 V and a bias current of 25 μA or 15 μA. The power consumDtion was less than 0.5 rnW

关 键 词：全并行模数转换器 数字采样保持 CMOS工艺 

分 类 号：TN432[电子电信—微电子学与固体电子学]