一种基于65 nm CMOS工艺的3抽头前馈均衡器  

A 3-Tap Feed-Forward Equalizer in 65nm CMOS

作　　者：周乃文[1] 多尔泰 王自强[1] 姜汉钧[1] 黄柯[1] 郑旭强[1] 袁帅[1] 吴凌涵 

机构地区：[1]清华大学,北京100086 [2]浙江大学,杭州310058

出　　处：《微电子学》2015年第6期764-768,共5页Microelectronics

基　　金：国家高技术研究发展计划资助项目(2011AA010405)

摘　　要：高速串行接口技术是当前高速数据传输的关键技术之一,而前馈均衡器(FFE)是高速串行接口中的重要模块电路。设计了一款工作在40Gb/s、用于高速串口发送端的前馈均衡器;分析了FFE求和模块、延时模块对均衡效果的影响;采用LC网络作为延时单元,并通过设计闭环反馈控制来控制延时时间,解决了高速均衡电路的延时实现问题。电路采用TSMC 65nm CMOS工艺进行设计和仿真,后仿真结果表明,在40Gb/s数据传输时,该3抽头FFE电路具有20dB的均衡能力;在TT_27℃工艺角、1.0V电源电压下,电路功耗为51.52mW。High speed serial interface technology is one of the key technologies in the current high speed data transmission field, and a feed-forward equalizer （FFE） is an important high speed serial interface module circuitry. A 3-tap FFE working in 40 Gb/s for the transmitter of high speed serial circuit was designed. The effects of summing circuit and delay element on the equalizer＇s performance were analyzed. The delay cell based onLC network and closed loop feedback were used to obtain the lowest power consumption and the best equalizer performance. The circuit was designed and simulated in TSMC 65 nm CMOS process. The simulation results showed that the FFE had a balance capacity of 20 dB at 40 Gb/s input rate, a power consumption of 51.52 mW at TT 27℃ process corner and 1.0 V power supply.

关 键 词：前馈均衡器 高速串行接口 LC网络延时 闭环反馈 模拟电路 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN715