一种1GHz多端口低功耗寄存器堆设计  

A 1GHz multi-port low-power register file design

作　　者：李娇[1,2] 王良华[1] 毕卓[1,3] 刘鹏[1] 

机构地区：[1]上海大学微电子研究与开发中心,上海200072 [2]上海大学新型显示技术及应用集成教育部重点实验室,上海200072 [3]上海大学机电工程与自动化学院自动化系,上海200072

出　　处：《计算机工程与科学》2015年第12期2222-2227,共6页Computer Engineering & Science

摘　　要：超标量处理器中的寄存器堆通常采用多端口结构以支持宽发射,这种结构对寄存器堆的速度、功耗和面积提出了很大的挑战。设计了一个64*64bit多端口寄存器堆,该寄存器堆能够在同一个时钟周期内完成8次读操作和4次写操作,通过对传统单端读写结构的存储单元进行改进,提出了电源门控与位线悬空技术相结合的单端读写结构的存储单元,12个读写端口全部采用传输门以加快访问速度。采用PTM 90nm、65nm、45nm和32nm仿真模型,在Hspice上进行仿真,与传统单端读写结构相比较,所提出的方法能够显著提升寄存器堆的性能,其中写1操作延时降低超过32%,总功耗降低超过45%,而且存储单元的稳定性也得到明显改善。Register files in superscalar processors usually adopt the multi-port structure to support the wide issue, however, this structure brings in problems such as prolonging access speed, increasing in silicon areas and higher power consumption. We design a 64 ＊ 64 bit multi-port register file which can concurrently accomplish 8 read operations and 4 write operations in one single clock cycle. We improve the conventional single-ended memory cell structure and purpose a new structure, which combines the power-gating and the bit-line floating techniques, and the transmission gate is used in all ports to accelerate the access speed. Simulations are conducted on Hspice with PTM 90 nm, 65 nm, 45 nm and 32 nm technology models compared with the conventional single-ended structure, the proposed method can significantly improve the performance of register files, the delay of write logic 1 decreases more than 32 %, and the to- tal power consumption decreases more than 45%; the stability of memory cells is also improved.

关 键 词：寄存器堆 单端结构 电源门控 位线悬空 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]