一种CMOS新型ESD保护电路设计  

Design of a new ESD protection circuit for CMOS device

作　　者：沈放[1] 陈巍[1] 黄灿英[1] 陈艳[1] 

机构地区：[1]南昌大学科学技术学院,江西南昌330029

出　　处：《现代电子技术》2015年第24期128-131,共4页Modern Electronics Technique

基　　金：江西省教育改革课题(JXJG-11-22-2);江西省教育改革课题(JXJG-13-28-6);江西省教育改革课题(JXJG-14-28-8);江西省教育厅青年科学基金项目(GJJ12165);江西省教育教学"十二五"规划课题(11YB452)

摘　　要：金属氧化物半导体(MOS)器件的缩放技术使集成电路芯片面临着严重的静电放电(ESD)威胁,而目前采用的ESD保护电路由于电流集边效应等原因,普遍存在着抗静电能力有限、占用较大芯片面积等问题。根据全芯片ESD防护机理,基于SMIC 0.18μm工艺设计并实现了一种新型ESD保护电路,其具有结构简单、占用芯片面积小、抗ESD能力强等特点。对电路的测试结果表明,相对于相同尺寸栅极接地结构ESD保护电路,新型ESD保护电路在降低35%芯片面积的同时,抗ESD击穿电压提升了32%,能够有效保护芯片内部电路免受ESD造成的损伤和降低ESD保护电路的成本。The scaling technology of the metal oxide semiconductor（MOS）device makes the integrated circuit chips face with serious electrostatic discharge（ESD） threats,and the problems of limited anti- static electricity capacity and occupying large chip area exist in the current used ESD protection circuit because of current crowding effect. According to ESD protection mechanism of the whole chip,a new ESD protection circuit was designed and implemented based on SMIC 0.18 μm technology,which has simple structure,small chip occupation area and strong capacity of anti-static electricity. The test results of the circuit show that,in comparison with the ESD protection circuit with same size and gate-grounded structure,the new ESD protection circuit can reduce the chip area by 35% while the anti-ESD breakdown voltage is increased by 32%. The circuit can effectively protect the internal circuits in the chip from ESD damage and reduce the cost of ESD protection circuit.

关 键 词：静电放电(ESD)保护 栅极接地NMOS 抗静电 电流集边效应 低成本 

分 类 号：TN43-34[电子电信—微电子学与固体电子学]