基于部分重构的SRAM型FPGA单粒子翻转模拟  

Emulation of Single Event Upsets in SRAM-based FPGA Using Partial Reconfiguration Techniques

作　　者：李林[1,2] 徐宇[1,2] 卢凌云[1,2] 贾海涛[1] 蔡刚[1] 李悦[1,2] 杨海钢[1] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院大学,北京100049

出　　处：《微电子学与计算机》2015年第12期95-99,104,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61271149);国家重点基础研究发展计划(2014CB744600)

摘　　要：介绍了一种基于部分重构技术的SRAM型FPGA单粒子翻转模拟方法.针对SRAM型FPGA的单粒子翻转特性,建立了一种能够模拟不同线性能量转移(LET)值和注量率(Flux)重离子入射的故障注入模型.该模拟方法可用于对SRAM型FPGA应用电路采用的抗辐照加固效果进行定量预评估,验证不同加固方案的有效性,同时还可减少辐照试验的次数,降低试验成本.基于Virtex-4SRAM型FPGA,针对三模冗余(TMR)的单粒子翻转加固方法进行了定量评估.评估试验结果表明,该方法较好地模拟了入射粒子LET值和系统电路失效率之间的关系,验证了三模冗余加固方法的有效性.An emulation method of single event upsets（SEUs）in SRAM-based FPGA by using partial reconfiguration techniques was presented.According to the characteristics of SEUs in SRAM-based FPGA,a fault injection model was built to emulate incident particles with different Linear Energy Transfer（LET）and Flux.Preliminary quantitative evaluation of hardening-by-design techniques can be done with this method,to enhance the effectiveness and pertinence,and reduce the time of radiation ground-testing which means less cost.A design with Triple Module Redundancy（TMR）based on Virtex-4FPGA was been evaluated,and the result showed that this method emulated the SEE and the failure rate was reduced with TMR.

关 键 词：SRAM型FPGA 单粒子翻转(SEU)模拟 部分重构 

分 类 号：TN4[电子电信—微电子学与固体电子学]