Schedule refinement for homogeneous multi-core processors in the presence of manufacturing-caused heterogeneity  

作　　者：Zhi-xiang CHEN Zhao-lin LI Shan CAO Fang WANG Jie ZHOU 

机构地区：[1]Department of Automation,Tsinghua University [2]Institute of Microelectronics,Tsinghua University [3]Research Institute of Information Technology,Tsinghua University [4]Tsinghua National Laboratory for Information Science and Technology,Tsinghua University [5]The School of Information and Electronics,Beijing Institute of Technology

出　　处：《Frontiers of Information Technology & Electronic Engineering》2015年第12期1018-1033,共16页信息与电子工程前沿（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.61225008;61373074;and 61373090);the National Basic Research Program(973)of China(No.2014CB349304);the Specialized Research Fund for the Doctoral Program of Higher Education,the Ministry of Education of China(No.20120002110033);the Tsinghua University Initiative Scientific Research Program

摘　　要：Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations,can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining(HASR) scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains.We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme,representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performance. A set of applications are designed to evaluate the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%.Multi-core homogeneous processors have been widely used to deal with computation-intensive embed- ded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations, can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining （HASR） scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains. We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme, representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performancc. A set of applications are dcsigncd to cvaluatc the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%.

关 键 词：Schedule refining Multi-core processor HETEROGENEITY Representative chip operating point 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]