一种FPGA在轨重构配置数据压缩算法  

Configuration Data Compression Algorithm for FPGA On-orbit Reconfiguration

作　　者：徐勇[1] 李珂[1] 冯国平[1] 陶利民[1] 庞波[1] 

机构地区：[1]北京空间飞行器总体设计部,北京100094

出　　处：《航天器工程》2015年第6期75-78,共4页Spacecraft Engineering

基　　金：国家重大科技专项工程

摘　　要：对现场可编程门阵列（FPGA）在轨重构配置文件压缩，可以大大减少遥控上注时间。为此，文章利用FPGA配置文件中0值较多的特点，结合游程编码（RLC）及字典编码的优势，提出一种FPGA在轨重构配置数据压缩算法，即结合零游程（Zeros Run Length，ZRL）编码的VLZW压缩算法（简称为ZRL—VLZW算法）。为减小航天器载计算机内存开销，使用索引迭代方式存储字典并限制字典长度。采用航天器常用FPGA多种资源占用比的配置文件，利用ZRL—VLZW、LZW和VLZW算法进行压缩测试比较。结果表明：ZRL-VLZW算法性能优于LZW算法和VLZW算法，可有效进行配置文件的压缩，使在轨重构注入数据上注时间减少为原来的1／20～1／3。The time for uploading FPGA on-orbit reconfiguration file can be reduced multiple times by using compression technology, so an algorithm called ZRL-VLZW （Zero Run Length VLZW） is proposed. It takes character of continues 0 data in configuration file to play the advan- tage of run length coding. In order to minimize the memory overhead of satellite computer, the en- try number of words dictionary is limited and iterative dictionary is employed. In the experi- ments,the performances of proposed algorithm are compared with LZW （Lempel Ziv Welch） and VLZW （Variable Lempel Ziv Welch） algorithm in compression configuration file of typical FPGAs. The results show that the proposed algorithm ZRL-VLZW can obtain higher compression ratio than that of LZW and VLZW. The time for uploading FPGA on-orbit reconfiguration file can be reduced to 1/20～1/3 by using the proposed algorithm.

关 键 词：现场可编程门阵列 在轨重构 配置数据压缩 

分 类 号：V446[航空宇航科学与技术—飞行器设计] TN791[电子电信—电路与系统]