素数域椭圆曲线密码加速器的VLSI实现  

VLSI implementation of elliptic curve cryptographic accelerator over GF(p)

作　　者：谢天艺 黄凯[1] 修思文[2] 唐从学 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,杭州310027 [2]中国计量学院光学与电子科技学院,杭州310018 [3]杭州朔天科技有限公司,杭州310012

出　　处：《计算机工程与应用》2016年第1期89-94,共6页Computer Engineering and Applications

基　　金：浙江省自然科学基金(No.LY14F020026);中央高校基本科研业务费专项资金(No.2013QNA5008);国家电网智能电网研究院项目(No.SGRI-WD-71-13-014)

摘　　要：分析了素数域椭圆曲线密码(ECC)算法的软件效率,针对软件效率较低的问题,对密码系统进行软硬件划分,提出了一种适用于椭圆曲线密码SoC的硬件加速器设计,并设计了密码SoC的结构。硬件加速器实现了素数域的点乘和素数检测,以少量的面积为代价提升了系统性能。密码芯片实现了SM2商用密码标准规定的6种算法。加速器基于HJTC 0.11μm eFlash单元库,面积约为0.6 mm^2。在50 MHz的频率下,192 bit非固定点乘运算性能为167次/s,256 bit非固定点乘运算性能为94次/s。实验结果表明,该加速器的单位面积性能高于其他同类设计。The software efficiency of Elliptic Curve Cryptography（ECC）algorithm over GF（ p） is analyzed. Against the disadvantages of the software implementation, the partition between software and hardware is given. A kind of hardware accelerator suitable for Sytem-on-Chip（SoC）is proposed, and the SoC architecture is designed. Hardware acceleration for both filed multiplication and Miller-Rabin primality test is implemented, which largely improves the performance of ECC at the expense of a little cost of area. The SM2 public key cryptographic algorithm is implemented on chip. Based on the HJTC 0.11 μm e Flash standard cell-library, the area of the accelerator is about 0.6 mm^2. The accelerator can execute167 operations per second for 192 bit unknown-point multiplication and 94 operations per second for 256 bit in 50 MHz.Experimental results show that the performance per unit area of the accelerator is higher than other approaches.

关 键 词：椭圆曲线 超大规模集成电路(VLSI) 点乘 素数域 SM2算法 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]