A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology  

作　　者：张彦辉 魏杰 尹超 谭桥 刘建平 李鹏程 罗小蓉 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China [2]Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China

出　　处：《Chinese Physics B》2016年第2期436-440,共5页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Grant Nos.61176069 and 61376079)

摘　　要：A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.A uniform doping ultra-thin silicon-on-insulator（SOI） lateral-double-diffused metal-oxide-semiconductor（LDMOS）with low specific on-resistance（R_on,sp） and high breakdown voltage（BV） is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate（AG） and back-side etching（BE）. The extended gate consists of a P– region and two diodes in series. In the on-state with VGD〉 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping（VLD） and the ＂hot-spot＂ caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.

关 键 词：LDMOS accumulation gate back-side etching breakdown voltage specific on-resistance 

分 类 号：TN305.7[电子电信—物理电子学]