低噪声快速建立的全片内LDO设计  

A fully on chip LDO with ultra low noise and fast set up

作　　者：陈远龙[1] 张涛[1] 王影[1] 张国俊[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《电子元件与材料》2016年第2期35-38,共4页Electronic Components And Materials

摘　　要：提出了一种集成于射频芯片的低噪声、快速建立的低压差线性稳压器(LDO)。分析了传统LDO的主要噪声源,在综合考虑芯片的噪声、静态电流和面积后,采用超低频低通滤波器,对LDO的输出噪声进行优化。基于SMIC 0.18μm工艺,采用Cadence软件对电路进行仿真。结果表明,10 Hz到100 k Hz之间的输出积分噪声电压为17μV,建立时间小于18μs,总静态电流为24μA,满足LDO的应用要求。A fully on chip low-dropout linear regulator（LDO） for RF application with ultra low noise and fast set up was presented. The main noises of LDO were analyzed based on the noise characteristics. Considering the noise in the chip, quiescent current and the area of chip, the ultra low frequency low pass filter was used to optimize the output noise of LDO. Based on SMIC 0.18 μm process, the simulation was conducted with Cadence software. Results show that output integrated noise voltage is about 17 μV ranging from 10 Hz to 100 k Hz, set up time is less than 18 μs and quiescent current is about 24 μA,which meets the requirements of LDO applications.

关 键 词：低压差线性稳压器 低噪声 快速建立 低静态电流 片内滤波器 集成 

分 类 号：TN432[电子电信—微电子学与固体电子学]