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机构地区:[1]College of Computer, National University of Defense Technology, Changsha 410073, China [2]National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China
出 处:《Chinese Physics B》2016年第3期283-289,共7页中国物理B(英文版)
基 金:Project supported by the National Natural Science Foundation of China(Grant Nos.61376109,61434007,and 61176030);the Advanced Research Project of National University of Defense Technology,China(Grant No.0100066314001)
摘 要:In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D- TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D- TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.
关 键 词:floating body effect in-line stacking SILICON-ON-INSULATOR source injection
分 类 号:TN304.12[电子电信—物理电子学]
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