0.13 μm CMOS Stacked-FET两级功率放大器设计  

Design of 0.13 μm CMOS Stacked-FET Two-Stage Power Amplifier

作　　者：王坤[1,2] 程新红[2] 王林军[1] 徐大伟[2] 张专[2] 李新昌[2] 

机构地区：[1]上海大学材料科学与工程学院,上海200436 [2]中国科学院上海微系统与信息技术研究所汽车电子工程中心,上海200050

出　　处：《半导体技术》2016年第2期102-106,共5页Semiconductor Technology

基　　金：国家科技重大专项资助项目(2012ZX02503-003)

摘　　要：基于TSMC 0.13μm CMOS工艺设计了一款适用于无线传感网络、工作频率为300~400 MHz的两级功率放大器。功率放大器驱动级采用共源共栅结构,输出级采用了3-stack FET结构,采用线性化技术改进传统偏置电路,提高了功率放大器线性度。电源电压为3.6 V,芯片面积为0.31 mm×0.35 mm。利用Cadence Spectre RF软件工具对所设计的功率放大器电路进行仿真,结果表明,工作频率为350 MHz时,功率放大器的饱和输出功率为24.2 d Bm,最大功率附加效率为52.5%,小信号增益达到38.15 d B。在300~400 MHz频带内功率放大器的饱和输出功率大于23.9 d Bm,1 d B压缩点输出功率大于22.9 d Bm,最大功率附加效率大于47%,小信号增益大于37 d B,增益平坦度小于±0.7 d B。Based on TSMC 0. 13 μm CMOS technology, a two stages power amplifier for 300- 400 MHz wireless sensor network was developed. The power amplifier driver stage used cascode configuration, and the output stage used 3-stack FETs configuration. A linearization technology was applied to improve conventional bias circuit, and the linearity of the power amplifier was enhanced. The supply voltage is 3.6 V, and the chip area is 0.31 mm×0.35 mm. The simulation of the proposed power amplifier was completed by the Cadence Spectre RF software. The simulation results show that the power amplifier achieves the saturated output power of 24.2 dBm, the maximum power added efficiency of 52.5% and small signal power gain of 38.15 dB at the operating frequency of 350 MHz. In the frequency range of 300-400 MHz, the power amplifier maintains the high saturated output power of larger than 23.9 dBm, 1 dB compression point output power of larger than 22.9 dBm, the maximum power added efficiency of larger than 47%, and the small signal power gain of larger than 37 dB with gain flatness of less than ＋0.7 dB.

关 键 词：CMOS 功率放大器 多管级联结构 线性化 无线传感网络 

分 类 号：TN722.75[电子电信—电路与系统]