基于CPLD的线阵CCD信号采集系统设计  

Design of Linear CCD Signal Acquisition System Based on CPLD

作　　者：董勇[1] 瑚琦[1] 高鹏飞[1] 

机构地区：[1]上海理工大学光电信息与计算机工程学院,上海200093

出　　处：《电子科技》2016年第3期154-156,共3页Electronic Science and Technology

摘　　要：文中基于复杂可编程逻辑器件设计一款高分辨率的线阵CCD信号采集系统。利用Verilog硬件描述语言进行了CPLD控制模块以及逻辑单元的程序设计,由图像专用A/D芯片中的相关双采样等特殊功能,实现了对CCD输出信号的噪声处理和模数转换,通过USB2.0接口实现了计算机终端采集和控制指令的实时传输。采用CPLD的设计方法具有驱动时序精确、采样速率快、抗干扰性强和输出信号稳定等特点。仿真结果证明,系统总体性能较好,上位机能正确显示采集到的CCD数据,噪声在允许的范围内,在不同的工作环境下,系统性能稳定。A high resolution linear array CCD signal acquisition system based on complex programmable logic device is designed in this paper. The Verilog hardware description language is employed in the CPLD control module and the logic unit of the program design. The special features of the A/D chip in the CCD are used to realize output signal processing and analog digital conversion. Real-time transmission is achieved through the USB2. 0 interface. The design method of CPLD has the characteristics of high accuracy,fast sampling rate,strong anti-interference and stable output signal. The simulation results show that the overall performance of the system is good stable under different working conditions with noise within the range of the system and correct display of the CCD data by the computer.

关 键 词：线阵CCD 复杂可编程逻辑器件 VERILOG HDL 

分 类 号：TN911.73[电子电信—通信与信息系统]