减速顶检测系统设计  

Detection System Design of Retarder

作　　者：邹兆光 苗中华[1] 陆鸣超 魏成雷 

机构地区：[1]上海大学机电工程与自动化学院,上海200072

出　　处：《工业控制计算机》2016年第1期46-47,共2页Industrial Control Computer

摘　　要：为了克服目前减速顶质量检测所存在的不足,设计完成减速顶检测系统。采用Altera公司的EP2C20Q240C8N作为主控芯片,并设计完成其他外围硬件电路。同时使用Verilog HDL语言进行程序编写。该系统能够对铁路上的减速顶在不反复拆卸的情况下实现质量检测等功能,减少事故发生,对改进既有检测方式方法具有积极的意义。In order to overcome the disadvantage of retarder detection system before,we have completed a new detection system of retarder.Chose EP2C20Q240C8 N which produced by Altera Corporation as the main chip,and design other peripheral hardware circuits.The program is written by using Verilog HDL.The system is able to achieve the detection of Retarder＇s quality without removed from railway and reduce the number of accidents.It has positive significance to change existing detection ways.

关 键 词：减速顶 检测系统 FPGA VERILOG HDL 

分 类 号：U284.63[交通运输工程—交通信息工程及控制]