一种高电源抑制比低噪声的带隙基准源  

A High Power Supply Rejection Ratio Low Noise Voltage Reference

作　　者：张涛[1] 陈远龙[1] 王影[1] 张国俊[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《电子技术（上海）》2016年第3期80-83,共4页Electronic Technology

摘　　要：基于SMIC 0.18μm CMOS工艺,设计了一种高电源抑制比低噪声的带隙基准源。此电路在3.3V电源电压下具有较好的温度系数,-40℃~125℃范围内的温度系数为8.6 ppm/℃,带隙基准电路输出电压约为1.195V。通过在基准中运放加入电源抑制比增强级电路提高中低频范围PSRR性能,在电路输出端再引入低通滤波器电路以提高中高频范围PSRR性能,并且低通滤波器有助于降低整个电路的噪声。采用Spectre软件进行仿真,结果显示,电源抑制比为-130.4@dc,-77.6@100KHz,输出噪声为24.8n V@100KHz。该带隙基准源电路非常适合于应用在高电源电压抑制比、低噪声的LDO电路中。Based on SMIC 0.18μm CMOS process, a high power supply rejection ratio（PSRR） low noise bandgap voltage reference was designed. The temperature coefficient of this circuit achieved 8.6ppm/℃ in the-40℃~125℃ temperature range when the input voltage was 3.3V, and the output voltage of the bandgap reference circuit wad 1.195 V. A PSRR enhance stage was inserted into op-amp to enhance PSRR in low frequency range, and low pass filter was inserted in voltage reference to improve PSRR performance in high frequency range, besides the low pass filter was helpful to reduce noise of the whole circuit. The circuit was simulated with Spectre software. Simulation results showed that the PSRR was-130.4d B at dc and-77.6d B at 100 KHz respectively, and output noise at 100 KHz was 24.8n V. The bandgap voltage reference circuit was suitable for the high PSRR and low noise LDO.

关 键 词：带隙基准 高电源抑制比 低噪声 电源抑制比增强级 低通滤波器 

分 类 号：TN432[电子电信—微电子学与固体电子学]