基于KMP串模式匹配算法的序列检测器的FPGA设计  

Design of sequential detector based on KMP algorithm and FPGA technology

作　　者：吴朝晖[1] 

机构地区：[1]安徽师范大学物理与电子信息学院,安徽芜湖241000

出　　处：《微型机与应用》2016年第6期6-8,11,共4页Microcomputer & Its Applications

摘　　要：基于FPGA设计一个能够检测出重叠匹配串的序列检测器。首先从KMP字符串模式匹配算法出发,推导出next函数值与序列检测器状态之间的关系,并针对匹配串重叠的情况进行修改,得到有限状态机的状态转换图,最后用VHDL语言描述并仿真验证。The paper designs a sequential detector based on FPGA technology,which is capable of detecting a overlapped binary sequence.Firstly,from KMP pattern-matching algorithm it deduces the relationship between the values of ＂next＂ function and finite state machine（FSM） states,makes some changes and gets a state transition diagram. At last it describes and simulates the circuit with VHDL language.

关 键 词：KMP模式匹配算法 序列检测器 FPGA VHDL 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]